1. Field of the Invention
The present invention relates to a semiconductor device, and particularly, to a configuration of an input circuit inputting an external signal to produce an internal signal. More particularly, the present invention relates to a configuration of an input circuit of a clock synchronous semiconductor memory device operating in synchronization with a clock signal.
2. Description of the Background Art
In order to interface with an external device, a semiconductor device is internally provided with an input circuit inputting a signal, as an interface circuit. Such a signal input circuit has not only a function of buffering a signal transferred from an external device to perform waveform shaping of the signal, but also a function of converting an amplitude and/or voltage level of the external signal depending on an interface of the external device to a signal corresponding to a signal amplitude of internal circuitry. As such an input circuit, one of input circuits with various configurations is used according to the external interface.
FIG. 25 is a diagram showing a first configuration of a conventional input circuit. In FIG. 25, the input circuit includes: a P channel MOS transistor (an insulated gate field effect transistor)PQ1 connected between a power supply node and an internal node ND1, and receiving an external signal EXS at a gate thereof; and an N channel MOS transistor NQ1 connected between internal node ND1 and a ground node, and receiving external signal EXS at a gate thereof.
On internal node ND1, an internal signal INS is generated through buffering of external signal EXS. A power supply voltage Vdd is applied to the power supply node.
The signal input circuit shown in FIG. 25 is a CMOS (Complementary MOS) inverter buffer and converts external signal EXS at TTL (Transistor-Transistor-Logic) level to internal signal INS at CMOS level. External signal EXS may be a signal at CMOS level.
In the configuration of the signal input circuit shown in FIG. 25, a input logical threshold voltage is determined by a function of a beta (xcex2) ratio of MOS transistors PQ1 and NQ1 and threshold voltages of MOS transistors PQ1 and NQ1. Therefore, by adjusting the input logical threshold voltage, external signal EXS at TTL level can be buffered to generate internal signal INS at CMOS level.
FIG. 26 is a diagram showing a second configuration of a conventional input circuit. In FIG. 26, the input circuit includes: a P channel MOS transistor PQ2 connected between a power supply node and a node ND2, and having a gate connected to node ND2; a P channel MOS transistor PQ3 connected between the power supply node and a node ND3, and having a gate connected to node ND2; an N channel MOS transistor NQ3 connected between node ND2 and a ground node, and receiving external signal EMS at a gate thereof; and an N channel MOS transistor NQ4 connected between node ND3 and the ground node, and receiving a reference voltage VREF at a gate thereof.
In the input circuit shown in FIG. 26, MOS transistors PQ2 and PQ3 constitute a current mirror circuit and a current the same in magnitude as a current flowing through MOS transistor PQ2 flows MOS transistor PQ3 (where both have the same size). When external signal EXS is higher than reference voltage VREF, a conductance of MOS transistor NQ3 is made larger than that of MOS transistor NQ4 and a larger current flows through MOS transistor NQ3, compared with a current flowing through MOS transistor NQ4. A current discharged through MOS transistor NQ3 is supplied from MOS transistor PQ2. Therefore, the current of the same magnitude as that supplied by MOS transistor PQ2 is transmitted to MOS transistor NQ4 through MOS transistor PQ3 (where both have the same size). Consequently, a voltage level of internal signal INS from node ND3 goes to H level.
When external signal EXS is lower than reference voltage VREF, to the contrary, a conductance of MOS transistor NQ4 is made larger than that of MOS transistor NQ3, and a drive current of MOS transistor NQ4 turns larger than that flowing through MOS transistor NQ3. Therefore, in this case, MOS transistor NQ4 discharges a larger current than that supplied from MOS transistor PQ3, to drive internal signal INS from node ND3 to L level.
It should be noted that in the input circuit shown in FIG. 26, a constant current source may be provided between a common source of MOS transistors NQ3 and NQ4 and the ground node.
In the case of the input circuit shown in FIG. 26, when external signal EXS is small in signal amplitude, and changes in a small amplitude with reference voltage VREF being a center, internal signal INS at CMOS level can be generated at high speed according to a logical level of external signal EXS. Specifically, when a signal line transmitting external signal EXS thereon is terminated with a terminating resistance and a signal amplitude of external signal EMS is made small, by use of the input circuit of a differential amplification type shown in FIG. 26, internal signal INS at CMOS level can be generated from external signal EXS of a small amplitude reliably.
FIG. 27 is a diagram showing a third configuration of a conventional input circuit. In FIG. 27, the input circuit includes: P channel MOS transistors PQ4 and PQ5 connected in series between a power supply node and a node ND4, and receiving external signal EXS and an internal control signal INCTL at their respective gates; and N channel MOS transistors NQ4 and NQ5 connected in parallel between node ND4 and a ground node with each other, and receiving external gate EXS and internal control signal INCTL at their respective gates.
In the NOR type input circuit shown in FIG. 27, when internal control signal INCTL is at H level, P channel MOS transistor PQ5 is an off state, while N channel MOS transistor NQ5 is an on state, and internal signal INS is fixed at a ground voltage level.
On the other hand, when internal control signal INCTL goes to L level, N channel MOS transistor NQ5 enters an off state, P channel MOS transistor PQ5 enters an on state, and therefore, a CMOS inverter is equivalently formed by MOS transistors PQ4 and NQ4 and internal signal INS is generated according external signal EXS.
The input circuit with the configuration shown in FIG. 27 operates dynamically according to internal control signal INCTL, and a timing at which external signal EXS is taken in is determined by internal control signal INCTL.
The input circuits shown in FIGS. 25 to 27 are appropriately selected for use in a signal input section of a semiconductor device depending on an interface and application thereof.
It should be noted that for a configuration of a input circuit, other different configurations can be available according to interfaces in use, not limited to the configurations as shown in FIGS. 25 to 27. For example, there is available a differential input circuit for an interface through which small amplitude signals are transmitted in the form of complementary signals.
In the event that a configuration of an input circuit is modified according to an individual interface, if a specific input circuit is formed in an individual semiconductor device according to an external interface to be used, such semiconductor devices are to be fabricated that are the same in configuration of internal circuitry and are different in configuration of the respective input circuits. In such a case, layouts have to be individually designed for the respective input circuits, leading to reduced design efficiency. Furthermore, another necessity arises for fabricating semiconductor devices different from each other only in configuration of input circuits in separate fabrication process steps, reducing a fabrication efficiency and in addition, making post-fabrication product management complicated.
Therefore, conventionally, the following process is employed, in which in a master process, input circuits accommodating for plural interfaces are formed in parallel on the same semiconductor chip and in a slice process, an input circuit to be used is connected to internal circuitry and to a signal input node according to an application of interest. Through use of such a master/slice process, a common semiconductor chip can be used for all external interfaces, resulting in improvement on fabrication efficiency. In addition, as for fabrication process steps as well, manufacturing processing is commonly applied on plural kinds of external interfaces in the master process, enabling the fabrication process to be simplified.
Where the master/slice process is employed, masks need to be changed depending on an input circuit to be used to form interconnections in the slice process. Therefore, in the slice process for forming an interconnection in an input circuit finally step, it is required to form an interconnection layer, patterning thereon and others, and a so-called turn around time (TAT) becomes longer, with the result of increased product cost.
Furthermore, another necessity arises for individually preparing specific masks for connection of an input circuit, resulting in increase in product cost, too.
Moreover, as shown in FIGS. 25 and 26, in order to generate an internal signal at high speed to drive the internal signal to a definite state at a faster timing, an input circuit operates at all times in accordance with an external signal. Consequently, such a problem arises that a current is consumed in an unnecessary period. For example, in a case of a semiconductor memory device, a data access is made when a chip select signal CS is activated, while no internal access is made and therefore, it is not particularly required to generate an internal signal when chip select signal CS is in an inactive state. Under such a situation of no access, however, the input circuit continues to operate to generate an internal signal to consume unnecessarily a current, leading to a problem of disabling achievement of a low current consumption. Such problem becomes more serious when a low power consumption mode is specified that requests a low current consumption, such as a sleep mode in a semiconductor memory device.
Furthermore, where an external signal is taken in to generate an internal signal in synchronization with a clock signal, it is required that a buffer circuit at a first input stage generates an internal signal at as fast a timing as possible to transmit the internal signal to internal circuitry. This is because it is necessary that a signal generated by the buffer circuit at the first input stage is latched or determined on a logic level thereof in synchronization with a clock signal.
It is an object of the present invention to provide a semiconductor device having an input circuit capable of reducing a turn around time, and capable of accommodating for plural different input interfaces.
It is another object of the present invention to provide a semiconductor device having an input circuit capable of reducing a consumed current without delaying a timing of generating an internal signal.
It is still another object of the present invention to provide a clock synchronous semiconductor memory device of a low power consumption.
A semiconductor device according to a first aspect of the present invention includes: a plurality of input buffers each different in form from other(s); and a program circuit for generating a signal alternatively setting the plurality of input buffers to an operable state. The plurality of input buffers are selectively set to an operable state according to an output signal of the program circuit and drive an internal node according to a signal received when made active.
A semiconductor device according to a second aspect of the present invention includes: a signal input circuit including an input buffer buffering a signal provided externally to generate an internal signal when activated; a register circuit for storing a signal specifying whether control on the input buffer by an operation activating signal instructing that the external signal is valid is to be enabled; and an activation control circuit for selectively activating the signal input circuit according to the operation activating signal and the stored signal in the register circuit. Where the stored signal in the register circuit indicates that control on the signal input circuit by the operation activating signal is enabled, the activation control circuit selectively activates the signal input circuit according to the operation activating signal. Where the stored signal in the register circuit indicates that control on the signal input circuit by the operation activating signal is to be disabled, the activation control circuit sets the signal input circuit to an operating state independently of the operation activating signal.
A semiconductor device according to a third aspect of the present invention includes: a buffer circuit for buffering a signal provided externally when activated; a clock buffer for generating an internal clock signal according to an external clock signal when a clock enable signal is activated; clock detection circuitry for detecting whether the clock enable signal is kept inactive for a prescribed period in a low power operating mode; and a control circuit for setting the buffer circuit and the clock buffer to an inactive state in response to a detection signal of the clock detection circuitry.
By selectively setting the plurality of input buffers each different in configuration from other(s) to be operable according to the output signal of the program circuit, a semiconductor device adaptable to any of external interfaces can be fabricated in the same fabrication process steps. Furthermore, in a post-fabrication test, a test on internal circuitry can be effected by selectively setting the plurality of input circuits operable using a tester.
Moreover, only an input circuit corresponding to a desired external interface can be operated through a mere program of the program circuit, thereby enabling reduction in turn around time as well as fabrication cost.
Furthermore, by setting whether or not the input circuit is to be controlled in accordance with the operation activating signal according to a stored signal in the register circuit, a semiconductor device of a low consumed current can be achieved readily, that is adapted to a usage application without modifying an internal configuration of the device to any extent.
Moreover, in the low power mode, when the clock enable signal is held in an inactive state for a period of a prescribed number of cycle(s), the buffer circuit and the clock buffer circuit are disabled. Consequently, since no operation of generating an internal signal according to an external signal is performed in the low power operation mode, a consumed current can be reduced more in the low power mode through ceasing of such unnecessary operation of the buffer circuits.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.